1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an improved gate structure of a flash memory device and a method of fabricating the same, which allows programming and erasing operations using a low applying voltage.
2. Description of the Background Art
FIG. 1 shows a layout of a conventional gate structure of a flash memory device, FIG. 2 shows a cross-sectional view taken along line II--II in FIG. 2, and FIGS. 3A-3E show cross-sectional views of the conventional gate structure illustrating a conventional method of forming the same.
As shown in FIG. 2, the conventional gate structure of a flash memory device includes a semiconductor substrate 1, a gate insulation film 2 formed on a portion of the substrate 1, a first polysilicon film 3 formed on the gate insulation film 2 and serving as a gate electrode, and a tunnel insulation film 4 formed over the substrate 1, the gate insulation film 2 and the gate electrode 3. The tunnel insulation film 4 is thinner than the gate insulation film 2.
The conventional gate structure further includes a second polysilicon film 5 serving as a floating gate, an inter-dielectric film 6 formed on the second polysilicon film 5, a third polysilicon film 7 serving as a control gate, an insulation film 8 formed on the third polysilicon film 7, and a leveling film 9 formed on the insulation film 8. The gate structure also includes a contact hole 10 for exposing an upper surface of the gate electrode 3, sidewall spacers 11a formed on the sidewalls of the contact hole 10, and a metallic layer 12 formed on the leveling film 9 and in the contact hole 10.
Referring to FIGS. 3A through 3E, the conventional method of forming the above-described gate structure of the flash memory device will now be described.
As shown in FIG. 3A, a gate insulation film is deposited on the substrate 1 by chemical vapor deposition (CVD) and patterned to form a gate insulation film 2. A first polysilicon film 3 is formed on the gate insulation film 2.
As shown in FIG. 3B, a thermal oxidizing process is performed on the substrate 1 and first polysilicon film 3 so as to form a tunnel insulation film 4 which is thinner than the gate insulation film 2.
As shown in FIG. 3C, a second polysilicon film 5, an inter-dielectric film 6, a third polysilicon film 7 and an insulation film 8 are sequentially formed on the tunnel insulation film 4. A boron phosphorous silicate glass (BPSG) is coated on the insulation film 8 and etched back to form a leveling film 9.
As shown in FIG. 3D, using an etching mask, portions of the leveling film 9, insulation film 8, third polysilicon film 7, inter-dielectric film 6, second polysilicon film 5 and tunnel insulation film 4 are etched to form a contact hole 10 therethrough. An insulation film is deposited in the contact hole 10 and on the leveling film 9, and etched back using CVD to form sidewall spacers 11a on the sidewalls of the contact hole 10.
As shown in FIG. 3E, a metallic layer 12 is formed on the leveling film 9 and in the contact hole 10, thereby completing the formation of gate structure of the conventional flash memory device.
In the conventional flash memory device, a negative voltage is applied to the gate electrode 3, a positive voltage is applied to the control gate 7, a positive low voltage is applied to a drain region (not shown), and a ground potential is applied to a source region. Thereafter, electrons are implanted from the gate electrode 3 into the floating gate 5 using a Fowler Nordheim (FN) tunneling method to program the device. A MOSFET (metal oxide silicon field effect transistor) of the flash memory device monitors the programming operation. The amount of electrons injected into the floating gate 5 depends on time. As more electrons are injected into the floating gate 5, the less current flows through the drain region which increase the threshold voltage of the device. Therefore, when programming is performed on a cell array, the threshold voltage of all of the cells being programmed can be controlled to converge to a certain value, automatically.
Meanwhile, when a bias (which is an opposite type to the bias condition applied to the device during programming) is applied to perform an erasure operation in the conventional flash memory device, the electrons accumulated in the floating gate 5 in accordance with the FN tunneling method are implanted into a source/drain region or a channel region, thereby increasing the current flowing through the drain and decreasing the threshold voltage of the device.
The conventional flash memory device, however, provides weak electric field between the gate electrode 5 and the control gate 7 in accordance with an applied bias voltage. As a result, there may occur at times erroneous operations when the electrons are not injected from the floating gate 5 to the control gate 7.
Furthermore, if the applied voltage is raised to a higher level, there is a problem of electrons tunneling from a data line (metallic layer) 12 directly to the control gate 7.